Memory controllers are designed to interface with memory in a computer system on behalf of one or more bus masters (e.g. processors, peripheral devices, video controllers, etc.). Bus masters are components of a computer system which perform various tasks within a computer system and communicate with other components of a computer system, including other bus masters, via a common system bus. A computer system in this context, as in known in the art, can be a system on chip (SoC), a desktop computer, portable computing device such as a personal digital assistant or other forms known in the art. Bus masters often require access to memory in a computer system for the reading and writing of data to perform their prescribed functions in response to a user, operating system, other software or hardware. The accessing of memory is generally handled by a memory controller, which performs the reading of data by retrieving data specified by a request submitted by a bus master and makes it available on the system bus for access by the requesting bus master. A memory controller performs the writing of data to memory by receiving a request to write to memory from a bus master and stores the data in computer system memory.
In some scenarios, a bus master may make requests to read or write data from memory that can be anticipated. For example, an LCD or video controller, when performing the task of updating or drawing the contents of an LCD or video display, typically submits a series of consecutive requests to read data from a range of sequential addresses in memory. Generally, an LCD controller submits these requests to a memory controller, which when the request is received fetches the data from the address specified in the request and delivers it to the LCD controller via the system bus of the computer system. Often, when an LCD controller submits an initial request to read from memory, the next request submitted to the memory controller can be predicted because it will likely submit a request to read data from the next sequential address in memory. Memory controllers as known in the art, however, generally do not have the ability to predict a bus master's subsequent requests to access memory. Therefore, after submitting each request to read from memory, an LCD controller must wait for a memory controller to decode its request, fetch the requested data from memory and make the requested data available on the system bus.
In the abovementioned scenario, the efficiency and performance of a computer system could be improved if the amount of time an LCD controller is forced to wait after submitting a request to read from memory until data is delivered by the memory controller is reduced. Typically, a memory controller, upon receipt of a request to read from memory from a bus master, will respond with a “wait” or a “split” signal, which causes the requesting bus master to wait, and often stall, until the requested data has been delivered. After sending a “wait” signal, the memory controller will then fetch the requested data from memory, which is known in the art as a process that can cause delay in the performance of the computer system. After fetching the data from memory, the memory controller will make the data available on the system bus for the requesting bus master.
Because after submitting a request to read data from memory a bus master must wait for the memory controller to fetch the requested data before receiving it, this is a cause of delay that lowers the performance and efficiency of the computer system. However, if a memory controller has the ability to predict or anticipate subsequent requests from a bus master after receiving an initial request from the bus master, the performance and efficiency of the computer system can be improved. Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.